Test Planning, C, Systemc, Shell, Verilog, Tcl, Python, power-aware verification using UPF, systemverilog, NoC bus and interconnect verification, assertions, transaction-level modeling, UVM-based testbench development, constrained-random verification, formal verification

Azure, Scrum, Agile, Java, Database Technologies, AWS, Kubernetes, Python, Docker, Git, data structures, DevOps principles, microservices architecture

Apis, Networking, Nosql, Linux, Perl, Distributed Systems, Agile, Ruby, Python, AWS, scalable test frameworks, Reliability Testing, CI CD

Perl, Python, Tcl, VPlan, Synopsys VCS, Synopsys VC Formal, JasperGold, Cadence simulation tools, AMBA protocols, Uvm, systemverilog

Google Cloud or Azure Experience, Google BigQuery, Python programming skills

Python, Tcl, Sta, RedHawk-SC, EMIR, Voltus

Java, Debugging, Research, Kotlin, Software Design, Python, Classifiers, AI ranking, Model deployment, reinforcement learning, Silfra Orchestration, Data Processing, Magit, QFlow, Superroot, Generative AI tools, Fine tuning, GWS plugins, Gemini, Model evaluation

Verilog, systemverilog, Rtl Design, Verification Manager, Test Bench

C, Pcie, Ethernet, SV, CXL, Uvm, UCIe, systemverilog

liberty , boundary scan , Svn, JIRA, DDR, Jtag, Pcie, Verilog, Scripting, System Verilog, Tcl, python, PHY-level IO interfaces, bump map pattern definition, pad ring planning, RTL, IO standards, lef, SERDES, EDA Tools, IEEE 1149.1, IO library cells, Isp, Orbit IO, DFT methodologies, flow automation, IO cell placement, CXL