Power EM IR-drop analysis, Synthesis, Full-chip hierarchical floorplanning, RTL-to-GDSII implementation, Linting, UPF-driven low-power design methodologies, Parasitic Extraction, Timing SI power closure

static timing analysis, Verilog, Python, Tcl, SDC development, Tempus, Cadence Innovus, simulation methodologies, Rtl Design, transistor-level concepts, Genus, digital circuit operation, custom layout fundamentals, place-and-route, multi-clock designs, Synthesis, digital design fundamentals, floorplanning, Physical Verification, systemverilog, CDC concepts, Timing Constraints, Liberty timing models, characterization concepts