Perl, Python, Tcl, VPlan, Synopsys VCS, Synopsys VC Formal, JasperGold, Cadence simulation tools, AMBA protocols, Uvm, systemverilog

Perl, Python, Tcl, Clock domain partitioning, Block and subsystem-level physical design flows, primetime, Power integrity and power-aware physical implementation, Clock gating, Fusion Compiler, Congestion analysis and resolution, Clock tree architecture, Tempus, Cadence Innovus, Skew management, Certus, Synopsys ICC2, Timing closure and constraint management

static timing analysis, Floor Planning, Synthesis, Makefile scripting, physical design CAD flow, physical design verification, Mentor Calibre, Power Distribution, Cadence Innovus, Cadence Genus

synopsys primetime , Tcl, Python, Perl, SI noise analysis, AOCV, MMMC methodologies, timing exceptions, POCV, OCV, clocking methodologies

Azure - AKS, Python, Sql, Github, Docker, Arm

Perl, Scripting Languages, Python, Computer Engineering, Tcl, ASIC RTL2GDS implementation, Electrical Engineering, Computer Science

Software Release Management, Shell scripting, Deployment Git, WLAN standards IEEE 802.11, Automation using Python