Perl, Python, Tcl, VPlan, Synopsys VCS, Synopsys VC Formal, JasperGold, Cadence simulation tools, AMBA protocols, Uvm, systemverilog

Pcie, Systemc, Jenkins, Python, Perl, MATLAB, Design Verification, DV, Design Verification Lead, IP Verification, Subsystem Verification, systemverilog, Uvm, formal verification, Functional Verification, Constraint Random, Coverage Closure, Verification Plan, Specman E, Xcelium, Vmanager, Verilog-A, RNM, C Modelling, ISO 26262, Semiconductor, Pre-Silicon Verification

memory controllers , C, Python, On-chip interconnect NoC, PHY, Ace, ARM AMBA protocols, Uvm, FPGA prototyping, systemverilog, Simulation and emulation flows, Security IPs, Axi, APB, NPU ML accelerator cores, AHB

Azure, Scrum, Agile, Java, Database Technologies, AWS, Kubernetes, Python, Docker, Git, data structures, DevOps principles, microservices architecture

Usb, Vcs, DDR, Pcie, Perl, Ethernet, Shell scripting, Python, Tcl, Xcelium, Uvm, systemverilog, Questa

Apis, Networking, Nosql, Linux, Perl, Distributed Systems, Agile, Ruby, Python, AWS, scalable test frameworks, Reliability Testing, CI CD

C, Pcie, Ethernet, SV, CXL, Uvm, UCIe, systemverilog

test environments , scoreboard , C, Soc Architecture, Shell, Verilog, Test Cases, Sequencers, Mixed signal designs, Debugging RTL and Gate simulations, Industry-standard simulators, Agents, Revision control systems, Verification testbenches, Testbenches, Regression systems, Verification methodology, Directed and constrained random verification methodology, Monitors

Python, Tcl, Shell scripting, Debugging, Perl, Uvm, systemverilog, Mixed-Signal Verification