Verilog, LINT, Synthesis, spyglass, cdc, RDC, Timing, Ethernet protocols IP, PPA optimization, RTL optimization, systemverilog

conformal lec , Perl, Verilog, Python, Tcl, VC spyglass, IPXACT, IORING, LINT, Formality, VSI, UPF, Design Partitioning, Phys GPIOs, SoC IP level Integration, RTL Coding

Perl, Verilog, Python, Makefiles, RTL Build flows, Chip Design Functions, SoC Verification, Physical Design, Rtl Design, Dft, Synthesis, System-On-Chip design implementation flow

Tcp Ip, Pcie, Perl, Shell scripting, Ethernet, RDMA IPs, VCS simulation tool, Silicon IP development process methodologies, Verilog RTL design, Design for Test methodologies, DMAs, NVMe based Storage IP

Automation Frameworks, Sta, LINT, Memory operation, Synchronous design concepts, power analysis, SoC design flows, CMOS Circuit Design, Rtl Design, spyglass, Synthesis, device physics, CDC methodologies

Python Scripting, Git, PrimeTime or equivalent tools, Modern SOC tools including Spyglass, Version control systems such as Perforce, ASIC design flow, Low power digital design and analysis, Digital Design, C embedded experience, VCS simulation, Cadence Conformal, ICManage, ASIC design in sub-20nm technology nodes, Questa CDC, RTL design in Verilog, Circuit timing STA

Debugging, System Verilog, 5G LTE, Uvm, AMD Zynq RFSoC, FPGA RTL design, Wi-Fi, Sta, VHDL, high-speed packet processing, DSP fundamentals, 5G, Synthesis, Altera Agilex, Timing Closure, Wireless Communication