Fpga, C, Soc Architecture, Verilog, Scripting Languages, digital logic design principles, systemverilog, logic synthesis techniques, RTL design concepts, ASIC design methodologies, low-power design techniques, emulation platforms, assertion-based formal verification

static timing analysis, Perl, Verilog, Python, Tcl, Rtl Design, Synthesis, Dft, ATPG, systemverilog

Version Control Systems, Tcl, Verilog, static timing analysis, Perl, Git, Shell, Perforce, Python, Scripting Languages, AHB, LEC, systemverilog, EDA Tools, LINT, Rtl Design, Synthesis, APB, Axi, SoC Architecture Design, SoC Integration, cdc, formal verification, AMBA protocols, Simulation