routing, place-and-route, timing and SDC constraint generation, floorplanning, low-power design methodologies, Physical Verification, repeater insertion, chip-level floorplanning, feedthrough topology planning, top-level port pin assignment, power-aware synthesis, Timing Closure, Placement

Toplevel Physical implementation, Processor designs

Cadence Innovus, STA concepts, Synopsys ICC2, Timing Closure, Physical Design, Logic synthesis concepts, Physical Design signoff requirements, Place Route

Tcl, Perl, Cadence EDI, Mentor Calibre, Synopsys ICC, verilog synthesis, Floorplan