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Key Responsibilities
Qualifications:
Job ID: 150608453
Skills:
Routing, floorplanning, Physical Verification, LVS, Analog Layout Design, Mixed-signal integrated circuits, ERC, Placement, DRC, Mentor Graphics, FPGA physical design, Cadence Virtuoso
Skills:
Cadence Virtuoso, Mentor Calibre, RF Analog layout techniques, Dfm, Matching parasitic reduction, Esd, EM analysis, RF analog circuit layout concepts
Skills:
Ant, Mentor Calibre, LVS, Latch-up, signal and clock shielding, EMIR, CMOS circuit theory, Esd, ERC, DRC, isolation techniques, Cadence Virtuoso, Reliability
Skills:
Ant, Mentor Calibre, LVS, Latch-up, signal and clock shielding, EMIR, ERC, CMOS circuit theory, Esd, DRC, isolation techniques, Cadence Virtuoso, Reliability
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