We're expanding our semiconductor engineering team and are looking for experienced Analog Mixed-Signal Layout Engineers to join an exciting long-term chip development project.
If you have a passion for custom analog layout, advanced process technologies, and high-performance mixed-signal IP development, we'd love to hear from you.
Location: Malaysia (Onsite)
Employment: Permanent position with ThunderSoft
Hiring Timeline:20 openings available. Recruitment is currently in progress and is expected to close by December 2026. Suitable candidates may be shortlisted before the closing date.
Key Responsibilities
- Perform full-custom layout design for analog and mixed-signal circuits using Cadence layout tools.
- Develop layouts for high-speed I/O circuits, including SerDes, DDR I/O, and other high-speed interfaces.
- Implement layouts for analog IPs such as PLLs, DLLs, LDOs, Bandgap References, and other precision analog circuits.
- Create and optimize I/O floorplans and power delivery planning to achieve performance, area, and reliability targets.
- Design and verify I/O ESD protection layouts and perform ESD-related layout analysis.
- Support advanced packaging implementation, including C4 bump planning and Redistribution Layer (RDL) layout.
- Ensure layouts comply with advanced process node design rules, reliability, matching, symmetry, and parasitic requirements.
- Perform layout verification, including DRC, LVS, ERC, and parasitic extraction (PEX), and collaborate with circuit designers to resolve layout-related issues.
- Work closely with design, verification, packaging, and process engineering teams throughout the development cycle.
Required Qualifications
- Bachelor's, Master's, or Ph.D. in Electrical Engineering, Electronics Engineering, or a related field.
- Experience in full-custom analog and mixed-signal IC layout.
- Strong knowledge and hands-on experience in one or more of the following:
- SerDes I/O, DDR I/O, or other high-speed I/O layouts
- PLL and DLL layout implementation
- LDO, Bandgap, and analog power management circuits/ power-delivery simulation
- Pure analog circuit layout
- I/O floorplanning and power delivery planning
- I/O ESD layout and analysis
- C4 bump and Redistribution Layer (RDL) implementation
- Proficiency with Cadence layout tools (Virtuoso Layout XL or equivalent).
- Solid understanding of DRC, LVS, ERC, parasitic extraction (PEX), electromigration (EM), IR drop, and reliability considerations.
- Strong knowledge of analog layout techniques, including device matching, common-centroid layout, shielding, guard rings, symmetry, and noise isolation.
Preferred Qualifications
- Experience with advanced semiconductor process technologies of 7nm or below.
- Hands-on layout experience in Samsung 5nm or below process technologies is a strong advantage.
- Familiarity with advanced packaging technologies and high-speed interface layout optimization.
- Experience collaborating with analog circuit designers from floorplanning through silicon validation.
Experience Levels
We are hiring engineers across multiple levels:
- 2–4 years
- 4–6 years
- 6–8 years
- 8+ years
Why Join Us
- Work on next-generation semiconductor products using advanced process technologies.
- Exposure to leading-edge Analog and Mixed-Signal IP development.
- Be part of a rapidly growing engineering team with 20 openings.
- Long-term career opportunity with excellent technical growth.
- Collaborate with experienced global engineering teams on challenging silicon projects.
If your experience matches the above, we'd love to hear from you. Please apply directly or send me your latest CV for a confidential discussion.
Recruitment is expected to close by December 2026. As interviews are conducted on a rolling basis, early applications are highly encouraged.
