Back End Developer

Responsibilities:

1. APR/STA senior engineers are responsible for completing the digital backend work from netlist to GDS, at the TOP or block level, including PR (place and route), STA (static timing analysis), PV (physical verification), PA (power analysis), and other tasks.

2. Collaborate with digital front-end engineers to debug issues such as timing, SDC, UPF, etc., and complete block-level or TOP PD work with moderate difficulty or above

3. pre/post mask eco

4. Collaborate with the design team to evaluate and optimize the digital area

Job Requirements:

1. Microelectronics-related major, bachelor's degree or above

2. More than 7 years of work experience, familiar with the complete design process from Netlist to GDS

3. Proficient in using one or several sets of design tools related to Innovus/ICC2, PT/computers, lec/form, starrc/QRC, PTPX/volt, caliber, etc

4. Experience in successfully tapping out chips with a process size below 14nm is preferred, and experience in working with low-power design chips is preferred

5. Experience in TOP P&R work is preferred (top-level partition, bump assignment, RDL routing, ESD plan, feedthrough inserting, pin assignment, etc)

6. Priority given to those with TOP STA experience

7. Equipped with PCIE, DDR, and other high-speed interfaces, P&R experience is preferred

8. Good English reading, writing, and communication skills

9. Possess innovative ability and team spirit.