Job Description:
Responsibilities include (but are not limited to):
- Custom Layout & Memory Design: Create custom transistor-level layouts for memory macros, including SRAM, flash memory, and peripheral circuits. Implement high-density memory array techniques with strict symmetry and matching.
- Floorplanning & Optimization: Collaborate with circuit designers to define chip floorplans, power grids, and signal routing to meet area and performance targets.
- Layout Verification: Perform and debug physical verification, including DRC (Design Rule Check), LVS (Layout vs. Schematic), ERC (Electrical Rule Check), and latch-up prevention.
- Reliability & Parasitics: Execute EM/IR (Electromigration and IR Drop) analysis and parasitic extraction (PEX) to ensure performance requirements.
- Tooling: Use EDA tools, specifically Cadence Virtuoso XL/GXL and Mentor Graphics Calibre.
Requirements
- Bachelor's degree in Electrical Engineering, Computer Engineering, or a related field.
- Minimum 5+ years of experience in custom layout design and mixed signal circuits.
- Strong knowledge of SRAM/DRAM/flash layout techniques, including memory array structure and peripheral circuits
- Proven expertise in physical verification using LVS (Layout Versus Schematic) and DRC (Design Rule Check) tools.
- IProven experience with advanced CMOS process technologies (e.g., 16nm, 7nm, 5nm).
- Deep understanding of parasitic reduction, matching techniques, ESD, and shielding techniques.
- Experience with Cadence Virtuoso Layout Suite or similar EDA tools is a must.
- Excellent problem-solving and analytical skills.
