Design Verification Engineer

Job Title: Staff / Senior Design Verification Engineer

Job Responsibilities:

1. According to the design requirements, architecture, and specifications, develop verification plans and schedules

2. According to the verification plan and schedule, set up an IP or SoC verification environment, develop and debug verification cases, checker mechanisms, etc

3. Analyze and locate the reasons for the testcases failure, assist designers in locating and solving problems

4. Testcases regression, collect and analyze code and functional coverage, and achieve coverage convergence

5. Verification quality activity inspection, ensure verification completeness, and output verification report

6. Improve verification efficiency, such as developing verification components, automating verification scripts, and implementing efficient verification methods

Job Requirements:

1. More than five years of verification work experience, with rich experience in IP or SoC verification, familiar with the verification process

2. Proficient in Verilog, system verilog, proficient in scripting languages such as Perl and Python is preferred

3. Proficient in UVM verification methodology, be able to independently build and debug IP or SoC validation environments

4. Strong initiative, sense of responsibility, serious and meticulous work, and good teamwork spirit

5. Priority will be given to those who meet the following conditions:

5.1 Controller or PHY (Serdes, PCIE, DDR, HBM, etc.) verification experience with high-speed interfaces is preferred for admission

5.2 Experience in verifying CPUs such as ARM or RISCV is preferred for admission

5.3 Experience in verifying on-board MCU or AI SoC is preferred for admission

5.4 Experience in verifying efficiency improvement, priority admission