Experience Level: 5+ years
Location: Penang
Job Description:
We are seeking a motivated and detail-oriented Design Verification Engineer to join our team. The ideal candidate will have hands-on experience in System Verilog and UVM, along with a solid understanding of verification methodologies and testbench development.
Key Responsibilities:
- Develop, implement, and maintain UVM-based testbenches for block-level and system-level verification.
- Create and execute test plans, write test cases, and analyze simulation results.
- Debug RTL and testbench issues using waveform analysis and simulation tools.
- Collaborate closely with design, architecture, and validation teams to ensure comprehensive functional coverage.
- Contribute to continuous improvement of verification methodology and automation.
Required Skills and Qualifications:
- Proficiency in System Verilog and UVM.
- Strong understanding of digital design fundamentals and verification methodologies.
- Minimum 5 years of experience in Design Verification.
- Good analytical and debugging skills.
- Familiarity with industry-standard EDA tools (e.g., Mentor QuestaSim, Cadence Xcelium, Synopsys VCS).
Preferred Qualifications:
- PCIe protocol knowledge is a plus but not mandatory.
- Exposure to coverage-driven verification and scripting (Perl, Python, or Shell).
- Experience with version control and continuous integration flows.
Soft Skills:
- Strong communication and teamwork abilities.
- Self-motivated, proactive, and eager to learn.
Contact:
Anna - WhatsApp +84935059669 - Email: [Confidential Information]
