Design Verification Engineer (Junior& Senior)

Requirements: -Bachelor Degree or M.S. in Electrical Engineering or Microelectronics.

- Experience with pre-silicon UVM experience 

The candidate should have good understanding on ASIC/SOC design flow and should have:  

1. Strong coding with Verilog and SystemVerilog 

2. Good knowledge of design verification methodology UVM. 

3. Many experiences with sequence creation, functional cover groups and assertion coding. 

4. Strong C/C++ software development experiences 

5. Be familiar with scripting language, such as Perl, C shell, Makefile, Ruby 

Add on 

• Familiarity with industry-standard high-speed protocols – USB Technical Skills/Expertise:- 

o USB 3.0, 3.1, 3.2, or USB4 protocols; 

o USB device and host controller; 

o USB protocol analyzer/debugging tools; 

o USB compliance testing 

• Familiarity with use of Software and Tools on USB/PCIe technologies or protocols:- 

o Synopsys VC Verification IP (VIP) for USB; 

o USB traffic generators and checkers; 

o Oscilloscopes for signal validation 

• Performed USB-IF compliance testing

Working Location: Bayan Lepas, Penang