Search by job, company or skills

Design Verification Engineer

ust malaysia
1-6 Years
Penang, Malaysia
  • Posted 17 hours ago
  • Be among the first 10 applicants

Job Description

Job Responsibilities:

  • Be part of a team verifying complex IPs and driving them to closure against challenging milestones.
  • Build verification environments and UVM/OVM testbenches based on chip requirements.
  • Work across RTL, power-aware, and gate-level verification.

Requirement:

  • Bachelor's degree (or higher) in Electrical/Electronic Engineering or related.
  • 1-6 years of hands‑on experience in digital IP verification using SV/UVM or similar methodologies.
  • Solid knowledge of ASIC verification concepts.
  • Bonus if you've dabbled in scripting (Perl/Python) or have database know‑how.
  • Willing to relocate and work in Penang, Malaysia

More Info

Job Type:
Permanent Job
Industry:
Other
Function:
Engineering
Employment Type:
Full time

About Company

Job ID: 153455985

Last Updated: 30-08-2026 01:50:04 PM
Homejobs in PenangDesign Verification Engineer

Similar Jobs

FPGA Silicon Design Verification Engineer

Altera
Penang, Malaysia

Skills:

Git, Perl, Python, Tcl, Functional Coverage, Regression Automation, Uvm, systemverilog, SVA

Design Verification Engineer

Inotec AMD
Penang, Malaysia

Skills:

Design Verification, object-oriented programming, Uvm

Graduate Talent (E-Core Design Verification Engineer)

Intel Corporation
Malaysia, Penang

Skills:

C, System Verilog, Python, verification tools and methodologies, Uvm

Design Verification Engineer

ThunderSoft
Malaysia, Penang

Skills:

Makefile, Verilog, Ruby, C Shell, C, Perl, Uvm, systemverilog

Beware of Scammers

We don’t charge money for job offers

Know More