DFT Engineer

Responsibilities:

• Implementing and optimizing boundary scan, MBIST, test logic insertion, and JTAG solutions.
• Build verification environments and UVM & SV testbenches based on chip requirements.
• Developing and validating scan ATPG and compression methodologies.
• Conducting DFT and post-gate simulation processes to ensure design robustness.
• Generating and applying DFT constraints for efficient testing.
• Delivering effective test patterns and collaborating with the test team for ATE debugging.
• Utilizing EDA tools like Tessent to enhance test processes and efficiency.

Job Requirements:

• Possesses a Masters or Bachelors degree in Electrical Engineering or Computer Engineering.
• At least 4-8 years of relevant experience. Fresh graduates are welcome to apply.
• Proficiency in synthesis tools such as Genus or Design Compiler.
• Experience working closely with designers to create test plans and strategies.
• Proven ability to collaborate with implementation teams for DFT insertion and resolve DFT-related timing or congestion challenges.
• Highly driven and detail-oriented
• Fresh graduates are welcome to apply.