Job Details
Job Description:
As a DFX Design Engineer at Altera, you will be part of the specialized team responsible for ensuring that our next-generation FPGA products are manufacturable, testable, and debuggable. You will work on integrating hardware features that allow us to detect defects and diagnose failures in complex silicon architectures. This role bridges the gap between RTL Design and Manufacturing, providing a unique end-to-end view of the semiconductor lifecycle.
Key Responsibilities
- DFT Implementation: Assist in the insertion and verification of Design for Test (DFT) structures, including Scan chains, Memory Built-In Self-Test (MBIST), and Boundary Scan (BSCAN/JTAG).
- Pattern Generation: Help develop and simulate ATPG (Automatic Test Pattern Generation) to achieve high fault coverage for silicon manufacturing.
- DFD Integration: Support the integration of Design for Debug (DFD) features that enable post-silicon analysis and hardware-software co-debugging.
- Verification: Perform RTL and Gate-Level Simulations (GLS) to verify DFX logic functionality and timing.
- Automation: Develop and maintain scripts (Tcl, Python, or Perl) to automate DFX flows and improve engineering efficiency.
- Collaboration: Work closely with Front-End Design, Physical Design, and Post-Silicon teams to resolve testability and timing issues.
- Continuous Learning: Participate in design reviews and technical training to stay updated on industry standards (IEEE 1149.1, 1687, etc.).
Qualifications
Academic Credentials
- Bachelor's or Master's Degree in Electrical Engineering, Electronic Engineering, Computer Engineering, or Microelectronics.
- Minimum CGPA of 3.0/4.0 (or equivalent).
Technical Skills
- Hardware Description Languages: Proficiency in Verilog or SystemVerilog is essential.
- Digital Logic Design: Strong foundational knowledge of digital logic, state machines, and computer architecture.
- Scripting: Basic knowledge of Tcl, Python, or Perl for automation.
- EDA Tools: (Preferred but not required) Exposure to tools like Mentor Graphics (Tessent), Synopsys (Design Compiler/DFTMAX), or Altera Quartus Prime.
- Knowledge Areas: An understanding of basic DFT concepts (Scan, JTAG, BIST) from university projects or internships is a major plus.
Soft Skills
- Analytical Mindset: Strong problem-solving skills with high attention to detail.
- Communication: Fluent in English (written and spoken) to collaborate with global teams.
- Adaptability: A proactive learner who can thrive in a fast-paced, high-tech environment.
Job Type
Regular
Shift
Shift 1 (Malaysia)
Primary Location:
Penang 15, Penang, Malaysia
Additional Locations:
Posting Statement
All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.
