FPGA Validation Engineer

Key Responsibilities:

Perform RTL glue logic development to support FPGA-based system validation

Implement complete FPGA systems including:

Timing closure

Clock domain planning and management.

Pin assignments and I/O configuration

Execute FPGA hardware bring-up and functional testing on targget platforms

Debug and validate system-level functionality using FPGA platforms

Requirements:

Bachelor's or Master's degree in Electrical/Electronic Engineering or related field.

6-8 years of experience in FPGA design, validation, and bring-up.

Strong RTL coding skills using Verilog/SystemVerilog or VHDL.

Proficient in FPGA toolchains (e.g., Xilinx Vivado, Intel Quartus).

Solid understanding of synthesis, place and route, and static tinming analysis.

Hands-on experience with lab equipment and FPGA hardwaretesting.

Familiarity with scripting languages such as TCL or Python is a pplus

Experience working on Xilinx or AMD FPGA platforms is preferred.