IP RTL Designer / IP or SOC Validation Architect / IP or SOC Validation Engineer

Company Description SkyeChip is a Malaysia-based design company focused on delivering cutting-edge IP and IC solutions for artificial intelligence and high-performance computing. Founded in 2019 by a team of world-class IC designers, the company brings together an average of more than 15 years of experience in multinational corporations and a strong track record in CPU, chipsets, SoC, and ASIC development. SkyeChip offers in-depth technical expertise across the full product lifecycle, including architecture, micro-architecture, logic design, circuit design, DFT, physical design, layout, test, and product engineering. The team culture emphasizes technical excellence, innovation, and the opportunity to contribute to advanced IP and ASIC products used in next-generation computing systems.

Role Description This is a full-time, on-site role based in Georgetown for an IP RTL Designer / IP or SoC Validation Architect / IP or SoC Validation Engineer. Day-to-day responsibilities may include defining and implementing IP and SoC architectures, developing RTL for complex digital blocks, and reviewing micro-architecture specifications for performance, power, and area targets. The role involves building and maintaining verification environments, creating test plans, writing test benches, and executing simulations to ensure functional correctness and robustness of IP and SoC designs. Team members collaborate closely with cross-functional groups such as physical design, DFT, and product engineering, participate in design and code reviews, and contribute to continuous improvement of design and validation methodologies and flows.

Qualifications

• Strong digital design foundation with experience in RTL design using hardware description languages such as Verilog or SystemVerilog, and familiarity with micro-architecture development for complex IP or SoC components.
• Competence in verification and validation, including testbench development, simulation-based verification, functional coverage, and debugging of IP or SoC designs using industry-standard EDA tools.
• Understanding of ASIC and SoC design flows, including synthesis, timing analysis, DFT concepts, and collaboration with physical design teams to meet performance, power, and area goals.
• Experience with script-based automation (e.g., Python, Perl, or Shell) to improve design, verification, and reporting workflows, and ability to work efficiently with version control and issue-tracking systems.
• Bachelor's or Master's degree in Electrical/Electronic Engineering, Computer Engineering, or related field, with strong analytical and problem-solving skills and attention to detail.
• Effective communication and collaboration abilities in a multidisciplinary engineering environment, with a willingness to learn, share knowledge, and mentor others when needed.
• Exposure to CPU, AI accelerators, high-performance computing architectures, or previous experience in IP or SoC development is an advantage.