Job Description
THE ROLE:
As a Systems Engineer of IPSE, own post-silicon bring-up/feature enable internal IPs for client SOC projects.
THE PERSON:
Owns developing and executing the IP-level bring-up and feature validation plans, attempts to reproduce, triage and debug all silicon issues.
KEY RESPONSIBILITIES:
• Define/maintain feature list.
• Defining and executing the overall PCIe/USB IP features test plan and post-silicon verify strategy, including required tools/scripts development.
• Debugging of PCIe/USB IP issues found during bring up, validation, and production phases of SOC programs, focus on dense server project mainly.
• Engage with post-silicon IP enablement efforts, join technical discussions to drive resolution on technical issues fix.
• Demonstrate IP End-to-End ownership.
PREFERRED EXPERIENCE:
• In-depth knowledge of PC architectures, good at PCIe/USB/ESPI/I2C/I3C protocol.
• Strong self-learning capability, strong individual analysis, hands-on working, problem solving skills.
• Strong hardware experience with board design and onboard debug skill.
• Good communication skills and English reading/writing skill. • Preferred strong programming/scripting skills (eg. C/C++, Python, Perl, Ruby, Assembly).
• Understand Verilog coding or DV simulation environment.
• Known software experience with operating system, kernel, BIOS, as a plus.
ACADEMIC CREDENTIALS:
• MSEE within 3-5 years, or BSEE within 5-10 years experience in digital ASIC/SOC design
• Must first-hand Bring up or debug experience: 5+ years on Post silicon, or IP/platform board validation.
