Lead Design Verification Engineer

Lead Design Verification Engineer (SoC Verification)

Location: Bengaluru, India

Experience: 5–10 Years

About the Role

We are looking for a Lead Design Verification Engineer to verify next-generation ARM-based SoCs with a focus on USB, SoC integration, and Low Power Verification. You will drive end-to-end verification from test planning to coverage closure while collaborating with architecture, RTL, and validation teams to deliver first-pass silicon success.

What You'll Do

• Lead functional verification of complex ARM-based SoCs and subsystem integration.
• Develop verification plans, testbenches, and reusable verification components using SystemVerilog/UVM.
• Verify USB 2.0/3.x protocols and SoC-level functionality.
• Perform Low Power Verification using UPF/CPF, including power-aware simulations.
• Drive regression, functional/code coverage, debugging, and verification closure.
• Collaborate with RTL, architecture, DFT, and physical design teams to resolve design issues.
• Contribute to verification automation and methodology improvements.

What We're Looking For

• 5–10 years of experience in SoC Design Verification.
• Strong hands-on expertise in SystemVerilog, UVM, and assertion-based verification (SVA).
• Experience verifying ARM-based SoCs and subsystem integration.
• Strong knowledge of USB protocols (USB 2.0/3.x).
• Hands-on experience with Low Power Verification (UPF/CPF) and power-aware verification flows.
• Solid understanding of AMBA AXI/AHB/APB interconnects and SoC architectures.
• Experience with simulation, regression management, coverage closure, and debugging.
• Proficiency in Python, Perl, or Shell scripting is a plus.

Qualifications

• B.E./B.Tech/M.E./M.Tech in Electronics, Electrical Engineering, Computer Science, or a related discipline.

Why Join Us

• Work on cutting-edge ARM SoCs powering next-generation computing platforms.
• Solve challenging SoC verification problems alongside world-class silicon engineers.
• Build reusable verification infrastructure and influence verification methodology across projects.