Executing high density Si layout designs across advanced packaging elements (EMIB, Interposer, Test Chips and more).
Creates custom layouts of Integrated Circuits (EMIB, Si Interposer, Full loop/Short loop Test Chips etc,) for a given specification and runs complete set of design verification tools for process design rules, electron migration, voltage drop (IR), ESD, and other reliability checks on the layouts.
Creates accurate designs that meet project needs, applying understanding of design manuals, established processes, layout elements, and basic electronic principles.
Designs and analyzes input bumps/floorplans, layout structures, signal routing, differential pair checks, power grid, DRC, LVS and performs all required verification on the layout blocks/top level.
Troubleshoots a wide variety of issues up to and including layouts and tool/flow/methodology used in Si layout design.
Requirements:
Fluent in Si custom layout design tools - Cadence Virtuoso Platform Works with project stakeholders to align on projects, schedule, provide updates, and resolve issues.
Good domain understanding in advanced Si Manufacturing nodes and advanced packaging structures.
Possess a Bachelors Degree in Electronics Engineering or relevant disciplines with 2+ years of experience in the related field
