Physical Design Engineer

Responsibilities:

• Responsible for high performance block implementation (RTL to GDSII).
• Perform block level floor planning, power grid implementation, APR placement, timing optimization, CTS and routing.
• Close the design to meet timing, power budget and area targets.
• Run physical verification flows (DRC/LVS/EM/IR), implement fixes to meet the requirements.
• Implement ECO's to address functional bugs, timing and physical verification violations.
• Responsible for generation and maintenance of block level STA constraints and perform STA signoA checks.
• Responsible for timing model generation and support successful integration of blocks into SOC.