We are currently partnering with a leading global player in the semiconductor industry to hire Physical Design Engineers who are passionate about working on next-generation chip development.
If you have experience in digital LSI/ASIC physical design and are looking to work on cutting-edge technologies with global engineering teams, this could be an exciting opportunity.
Key Responsibilities
- Execute digital LSI physical design activities across the full implementation flow, from logic synthesis through physical sign-off.
- Develop, optimize, and refine synthesis strategies to meet design, timing, area, and power objectives.
- Drive place-and-route (P&R) activities, including floorplanning, clock tree synthesis (CTS), routing, and physical design optimization.
- Perform static timing analysis (STA) and timing closure to ensure compliance with performance specifications.
- Conduct power integrity analysis and power-related validation to enhance overall design robustness and reliability.
- Carry out physical verification activities, including DRC, LVS, and sign-off quality checks.
- Work closely with cross-functional teams to address implementation challenges and support successful silicon delivery.
- Participate in technical reviews and process improvement initiatives to enhance design quality, efficiency, and execution.
Requirements
- Bachelor's Degree in Electrical Engineering, Electronics Engineering, Computer Engineering, or a related field.
- 3–10 years of practical experience in digital LSI or ASIC physical design.
- Strong hands-on knowledge of the complete RTL-to-GDSII implementation flow.
- Proficiency with leading EDA tools from Synopsys, Cadence, Siemens EDA, or equivalent platforms.
- Solid understanding of physical implementation, timing closure, optimization techniques, and design verification methodologies.
- Strong analytical thinking, debugging, and problem-solving capabilities.
- Effective communication and collaboration skills within multidisciplinary engineering teams.
- Experience with advanced process technologies such as 7nm, 5nm, 3nm, or more advanced nodes.
- Exposure to high-performance and/or low-power SoC and ASIC development projects.
- Experience owning design blocks, leading project deliverables, mentoring junior engineers, or serving as a technical lead is an added advantage.
