Physical Design Engineer(Graduate&Internship-MYS)

Responsibilities

• Block-level physical design of large-scale AI chip (Netlist to GDS out) for tapeout.
• Optimize timing, power, area, etc.
• Responsible for backend analysis: timing, power, power integrity, signal integrity, etc.
• Responsible for physical verification including DRC, LVS, ERC, Latchup, etc.

Qualifications

• Bachelor&aposs degree and above in Electrical Engineering, Computer Engineering, Computer Science, or a related field of study.
• Knowledge of digital IC timing & layout.
• Knowledge of digital IC backend design flow.
• Experience in IC backend design is a plus.