Physical Design Engineer

Requirements:

• As a IC Package Design Engineer, you will be responsible for executing high density package layout designs across
• Intel's product portfolios (Test Chips, CPUs, Chipsets, SoC designs, Test Vehicles and more)
• The responsibilities include but not be limited to:
• IC package layout design including
• o Routing feasibility studies
• o Signal breakout & full path routing, including Length matching (Group/ Diff Pair) for Low-Speed IOs and High-Speed
• IOs (e.g. DDR, PCIe, SERDES)
• o Power routing
• o Package Ballmap assignment
• o VSS Stitching (Vertical/ Horizontal)
• o Design rule checks (DRCs) and DRC cleanup (e.g. Mentor DRC and PLA eDRC)
• o Adhesion hole generation and touchup
• o Routing over void report generation and fixes
• o Return path report generation and cleanup
• Using the Mentor Graphics Xpedition PCB software to design the substrate in compliance with existing design rules,
• electrical requirements, and processes.
• Work together with assigned PDE to deliver Package design milestones on time and with the expected design
• quality.
• Requirement: