Role Description
- Carry out backend IC design physical implementation work (aka PNR) for advanced SoC/ASIC designs from SYN to GDS.
- The candidate must work closely with team members and interact with the product/IP architect, logic design engineer, DFX owner, and design automation engineer to ensure timely job delivery.
- Willing to travel (domestic/international), or relocate
Qualifications
- Bachelor's/Master's degree in Electrical or Computer Engineering
- 3+ years of experience in the semiconductor industry
- Familiar with Linux OS and proficient in scripting using shell, TCL, Perl, Python, or C++, etc
- Rich hands-on experience with industrial standard EDA tools and flow on synthesis, floorplanning, clock tree, static timing analysis, signal integrity, EM/IR analysis, ECO implementation, formality verification, and physical design verification. (e.g., Cadence and/or Synopsys; super user is a plus)
- Experience with SoC/ASIC design methodologies and tools
- Experience in complex clock design, clock gating, and power gating design methodology
- Excellent problem-solving and analytical skills
- Excellent written and verbal communication skills
- Experience in leading small teams and collaborating on large projects
- Experience in working in a global engineering environment would be a plus
To help us ensure a fair and thorough review process, applications for the same job role can be resubmitted only after three months. Kindly cooperate on this.
If you have any questions about your previous application, please don't hesitate to reach out to us at[Confidential Information]
