We are hiring experienced Physical Design Engineers to work on advanced SoC designs.
Key responsibilities:
- End-to-end physical design: Floorplan, PnR, CTS, routing
- Drive timing closure using STA (MCMM analysis)
- Fix setup/hold violations and optimize PPA (power, performance, area)
- Support DRC/LVS signoff and tape-out readiness
Requirements:
- 2+ years in Physical Design (PnR + STA)
- Hands-on with ICC2 / Innovus, PrimeTime / Tempus
- Strong understanding of timing, constraints (SDC), and closure
- Scripting: Tcl/Python/Perl is a plus
Ideal for engineers with proven SoC tape-out experience.
