Physical Design Engineer

power optimization , routing, Perl, Verilog, Python, Tcl, Synthesis, submicron process node technologies, Timing Analysis, power delivery methodologies, LVS, Power Estimation, formal verification, VHDL, layout verification methods, DRC, Placement, low-power design techniques, timing signoff, Clock Tree Synthesis

Physical Design, Design for manufacturability, Timing closure methodologies, Placement and routing techniques, Clock Tree Synthesis, Design rule checks

routing, Sta, CTS, ECO execution, Pv, floorplanning, Dfm, constraints synthesis, Dft, Si, Timing Closure, block-level PnR, Netlist to GDS flow

Unix, Perl, Linux, Tcl, Low power verification, Placement, floorplanning, power analysis, PNR implementation

layout verification , System Verilog, Computer Engineering, Tcl, ASIC Design, Electrical Engineering, Computer Science, design rules, low power designs