Location: Malaysia
Employment Type: Full-Time
Key Responsibilities:
- Working on 10nm/7nm/5nm or lower nodes designs with various customers.
- Responsible to understand and develop flow/methodology using Perl/TCL programming for PnR activities (Floor planning, Placement, CTS, and Routing).
- Expertise in solving lower node technology related problems for critical designs to achieve desired performance, area, and power targets.
- Provide training and technical assistance to peers/customers.
Preferred Experience:
- Experience in Top/Block level ASIC PnR implementation (RTL to GDSII).
- Tape-out experience in lower nodes like 3nm, 5nm, 7nm, 10nm and above.
- Hands-on experience in Synthesis, Floor planning, Placement, Clock tree synthesis, Optimization, Routing, Parasitic Extraction, Static Timing Analysis, IR drop analysis, Physical Verification (DRC/LVS/DFM, chip finishing) and Sign Off.
- Excellent communication and presentation skills, experience in collaborating with global teams.
- Experience in hierarchical designs and/or Low Power implementation is an advantage.
- Working experience on CAD tools from Synopsys, Cadence and Mentor Graphics tool set.
- Must be an initiative-taker and be able to drive tasks independently and efficiently to completion.
- Ability to provide mentorship and guidance to junior engineers and be an effective team player.
- Preferred Tool for PD:
- Cadence Innovus, Tempus, Calibre
