THE PERSON:
You are passionate about modern, complex processor architectures and bring deep expertise in physical implementation flows. You have experience in full-chip floorplanning, synthesis, place and route, timing closure, and power optimization. You are a collaborative team player with strong communication skills and a history of working across geographies and disciplines. You possess excellent analytical and problem-solving abilities, are eager to learn, and thrive in tackling complex design challenges.
KEY RESPONSIBILITIES:
- Extensive hands-on experience in floorplanning, placement, clock tree synthesis (CTS), routing, timing closure, and physical verification.
- Proficient in timing and SDC constraint generation and management; strong debugging skills are a plus.
- Solid understanding of low-power design methodologies, including power-aware synthesis and place-and-route; familiarity with voltage domain checks is advantageous.
- Proven experience in chip-level floorplanning, including feedthrough topology planning, repeater insertion, and top-level port/pin assignment.
- Tapeout experience across multiple projects.
PREFERRED EXPERIENCE:
- At least 8 years and above of experience in related field.
- Proficiency in EDA tools such as Design Compiler (DC) and Innovus/ICC2.
- Skilled in Static Timing Analysis (STA) tools and techniques.
- Strong grasp of floorplanning and layout techniques compliant with foundry design rules.
- Experience with scripting languages including TCL, Perl, and Python.
- Excellent communication skillswritten, verbal, and listening.
- Strong interpersonal skills; adaptable, collaborative, and a dedicated team player.
ACADEMIC CREDENTIALS:
- Bachelor's or Master's degree in Computer Engineering or Electrical Engineering.
