Physical Verification Engineer

Job Title: Staff/Senior Physical Verification Engineer

Job Responsibilities:

1. Responsible for the physical verification of chips from netlist to GDS, including DRC, LVS, ERC, etc;

2. Participate in the development and optimization of the verification process to improve verification efficiency and accuracy;

3. Work closely with the front-end design team and layout design team to ensure the accuracy and consistency of the design during the physical implementation phase;

4. Quickly locate and solve problems discovered during the physical verification process, and provide detailed reports and improvement suggestions;

5. Participate in the chip fabrication and mass production process to ensure that the physical verification results meet manufacturing requirements.

Job Requirements:

1. Master's degree holder with over 5 years of experience and bachelor's degree holder with over 7 years of experience in physical verification of digital chips;

2. Able to independently complete DRC and LVS analysis of complex chips, with successful chip fabrication experience preferred;

3. Proficient in physical verification tools such as Calibre, familiar with EDA tools such as Synopsys and Cadence;

4. Familiar with and able to apply design rules for different process nodes (such as 28nm, 14nm, and more advanced processes);

5. Proficient in scripting languages such as Tcl, Perl, Shell, etc., able to write automated scripts to improve verification efficiency;

6. Able to independently complete PV tasks under pressure, willing to explore new technological fields and knowledge.