Principal AI Chip Design Engineer

Responsibilities

. Lead RTL design and implementation for AI chip SoC and subsystems.

. Own key modules such as AI accelerator control logic, DMA, NoC/interconnect, memory subsystem, die-to-die/chip-to-chip interfaces, register blocks, interrupt, clock/reset, and low-power control.

. Define microarchitecture, RTL partitioning, interfaces, and implementation plans.

. Translate architecture and microarchitecture specifications into clean, reusable, synthesizable RTL.

. Lead SoC/IP integration, bus/interconnect integration, and top-level connectivity.

. Work with verification teams on test plans, simulation debug, coverage improvement, and design quality.

. Work with physical design teams on synthesis, timing closure, area, power, congestion, and ECO issues.

. Support FPGA/emulation, silicon bring-up, performance tuning, and post-silicon debugging.

. Drive design methodology, documentation, code review, and best practices.

. Mentor junior and senior engineers and provide technical leadership across teams.

Qualifications

. Bachelor's degree or above in EE,Computer Engineering, CS, or related fields.

. 8+ years of experience in SoC design, RTL design, ASIC implementation, or complex IP/subsystem design.

. Strong Verilog/System Verilog RTL coding skills.

. Deep understanding of SoC architecture, including AXI/AHB/APB, NoC, DMA, memory subsystem, clock/reset, interrupt, and register design.

. Familiar with ASIC design flow, including lint, CDC/RDC, synthesis, STA, timing closure, low-power checks, formal verification, and equivalence checking.

. Strong experience in SoC/IP integration, subsystem design, and top-level RTL design.

. Strong debugging skills in simulation, waveform analysis, emulation, FPGA, or silicon bring-up.

. Experience with AI accelerator, NPU, GPU,CPU, DSP, or high-performance SoC design is preferred.

. Strong ownership, technical leadership, communication, and cross-functional collaboration skills.