Principal Network-on-Chip (NoC) Microarchitect

Location (on-site): Malaysia (Penang)

Click on the link to APPLY: https://lnkd.in/gg595AaK

Role Summary

We are a fast-growing semiconductor company building next-generation on-chip and die-to-die interconnect technology for AI, high-performance compute, and chiplet-based systems. As data movement becomes the dominant bottleneck in modern SoCs, our network-on-chip (NoC) fabric is the backbone that determines the performance, power, and scalability of our customers silicon.We are looking for a Principal NoC Microarchitect to own the microarchitecture of our interconnect fabric end-to-end — from topology and protocol definition through RTL-ready microarchitecture, performance, and physical convergence. This is a deep technical leadership role for someone who has architected production NoC/coherent-fabric IP (comparable to the work done at companies such as Arteris and Baya Systems) and wants to define the fabric at the heart of leading-edge chips.

Key Responsibilities

• Fabric microarchitecture: Own the microarchitecture of coherent and non-coherent NoC fabrics —routers/switches, network interface units, buffering, and links — from concept to silicon.

• Topology & partitioning: Define network topology (mesh, ring, torus, crossbar, tree, hierarchical) and partition the fabric to meet bandwidth, latency, area, and power targets.

• Flow control & QoS: Architect flow control, virtual channels, arbitration, and QoS/priority schemes; guarantee deadlock, livelock, and starvation freedom across the network.

• Protocols & coherency: Specify protocol handling and bridging across AMBA AXI/ACE/ACE-Lite/AHB/APBand CHI, plus cache-coherency (MOESI-class) and memory-ordering semantics.

• Chiplet & die-to-die: Extend the fabric across dies — die-to-die links, UCIe/chiplet interfaces, and multi die coherency — for scalable chiplet-based systems.

• Performance modeling: Build and drive performance models (analytical and cycle-accurate/SystemC), run traffic and workload analysis, and close bandwidth/latency budgets under realistic congestion.

• Physical awareness: Partner with physical design on floorplan-aware, physically-aware topology, timing closure, wire congestion, and pipelining for high-frequency, large-die implementations.

• Technical leadership: Drive microarchitecture specs, design reviews, and trade-off analyses; guide RTL, DV, and integration teams to a correct, high-quality implementation.

• Cross-team NoC flow: Work closely with hardware and software teams to define, refine, and automate the end-to-end NoC creation and optimization flow — from architecture and topology capture through configuration, generation, and performance tuning.

• Customer & SoC engagement: Engage directly with customers and internal SoC teams to translate system requirements into fabric configurations and win designs.

• Design review & optimization:Review, benchmark, and recommend topology and configuration/setting changes to optimize both internal fabric designs and external (customer) NoC designs for bandwidth ,latency, area, and power.

Qualifications

• Experience: 15+ years designing SoC interconnect / NoC / cache-coherent fabric microarchitecture, withmultiple designs taken to production silicon.NoC fundamentals: Deep, end-to-end understanding of NoC architecture, topology, and flow — including routing algorithms, virtual channels, credit/flow control, arbitration, QoS, packetization, and deadlock avoidance.

• Protocols: Strong command of AMBA protocols (AXI, ACE, AHB) and CHI, and of cache coherency andmemory-consistency/ordering models.

• Performance: Proven ability to define and analyze performance — bandwidth, latency, and QoS — usinganalytical models and cycle-accurate simulation.

• Implementation awareness: Solid understanding of the RTL flow and physical implication ofmicroarchitecture (timing, area, power, congestion, clock/power domains).

• Education & communication: BS/MS/PhD in Electrical/Computer Engineering or equivalent; excellentwritten and verbal communication for specs and cross-team leadership.

Additional Advantages:

• Commercial NoC IP: Direct experience with commercial NoC IP or fabric platforms — e.g., ArterisFlexNoC/Ncore, Baya Systems WeaveIP, or in-house equivalents at CPU/GPU/AI-silicon companies.

• Chiplet & UCIe: Chiplet / multi-die systems, die-to-die interconnect, and UCIe.

• IP automation: Configurable/generator-based IP, software-defined fabric, or automation/EDA forinterconnect generation.

• Modeling & tooling: Modeling in C/C++/SystemC/Python; scripting for architecture exploration anddesign-space sweeps.

• Domains: Domain experience in AI/ML accelerators, HPC, automotive, or high-end mobile SoCs.