Principal/Sr Staff Physical Design Engineer

Role Description

This is a full-time on-site role for Principal/Sr Staff Physical Design Engineer (PD) in Penang, Malaysia. The engineer will be responsible for tasks such as Top floor planing, full physical design implemention RTL2GDSII flow, physical verification, timing and PI closure on a day-to-day basis.

Experience: 10+ years

Domain Expertise

Physical Design including:

Top/Block Floor-planning

Place and Route (PnR)

Clock Tree Synthesis (CTS)

Physical Verification (DRC/LVS)

Engineering Change Order (ECO) for Timing & PI Closure

Description

1.Execute Top and block floor-planning and placement, CTS and routing tasks for advanced tech nodes (16nm/7nm/5nm/4nm/3nm).

2.STA (Static Timing Analysis): Expertise in identifying and resolving timing violations using appropriate timing constraints.

3.Synthesis and Constraints: Deep understanding of synthesis flows and timing constraints management.

4.Identify and solve Calibre DRC/LVS issues efficiently.

5.Handle manual ECOs effectively, including:

6.Clock push/pull adjustments,

7.Net-delay insertion, and

8.Associated shorts cleanup.

9.Drive Power-Aware PD implementation using low-power design techniques.

10.Work independently on Syn/PnR/STA/PD/PV/PI Closure for live projects.

Technical Skills Required

1.Cadence Innovus hands-on experience is mandatory.

2.Proficiency in TCL scripting (key for automation in physical design tasks).

3.Strong understanding of low-power techniques and power-aware implementations.

Soft Skills & Expectations

1.Self-motivated with the ability to work independently with minimal supervision.

2.Team player, capable of collaborating with cross-functional design teams.

3.Comfortable handling complex design challenges and multi-tasking efficiently.

Please send your resume to: [Confidential Information]