Role Summary
Lead Advanced Packaging and Bump R&D strategy across Asia, driving technology development, transfer, and high-volume manufacturing (HVM) readiness for next-generation semiconductor packaging solutions.
Key Responsibilities
- Define and execute Advanced Packaging and Bump R&D roadmaps across Malaysia, China, and the Philippines.
- Lead technology transfer, qualification, and HVM deployment of packaging and bumping technologies.
- Drive development of advanced packaging solutions including WLCSP, Cu Pillar, C4 Bump, RDL, UBM, TSV, and wafer-level integration technologies.
- Lead process innovation initiatives involving DBG, DAG, wafer thinning, die strength optimization, and advanced metallization schemes.
- Develop and qualify new materials and processes to improve cost, performance, reliability, and manufacturability.
- Support next-generation packaging architectures for AI, high-performance computing, and analog applications.
- Partner with global engineering, manufacturing, quality, and business teams to ensure successful technology deployment.
- Build, mentor, and lead a high-performing packaging development team while driving technical excellence and innovation.
Qualifications
- Bachelor's, Master's, or PhD in Engineering, Materials Science, Semiconductor Technology, or related field.
- Extensive experience in Advanced Packaging, Wafer-Level Packaging, Bumping, and Semiconductor Process Integration.
- Proven track record in technology development, technology transfer, and HVM ramp-up.
- Strong leadership, stakeholder management, and cross-functional collaboration skills.
- Experience leading global or multi-site engineering projects and teams.
