Senior Analog Layout Engineer
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Job Description: Analog Layout Engineer
Key Responsibilities/Preferred Experience:
The role involves execution in the field of full custom layouts in cutting edge technology nodes. It will require a good layout electrical parameter knowledge along with quick learning capabilities.
Candidate should be able to handle sub cells/leaf cells that are needed to build IP/macro using CAD tools
Chip level integration, physical verification and electricals closure
Candidate will be exposed/experienced to various other fields of custom layout
Custom layout expertise in lower technology
Digital, Analog and mixed signal layout.
Good understanding of reliability concepts
Good understating of layout electrical parameters and closure
This is for Analog Layout Engineers having exp in custom block layout like PLL, Bandgap, ADC, DAC etc. and Virtuoso, Calibre, DRC, LVS
Requires TSMC 3nm and 2nm 3-way NDA in place
3-8 years of experience required
Job ID: 153724195
Skills:
Synopsys IC Validator, Calibre DRC LVS PEX, high-speed analog and mixed-signal layout design, Custom Compiler, LVS, Cadence Pegasus, DRC, Cadence Virtuoso Layout Suite, ERC checks, 7nm FinFET technology
Skills:
Routing, Pvs, PERL, Tcl, R3D, PEX, LVS, Layout Techniques, Verification, Skill Programming, CAD Tools, Calibre, Analog Layout, ERC, VCAR, DRC, VSR, virtuoso
Skills:
synopsys tools , Analog Circuit Design, Mentor Siemens Calibre, Physical Verification, ERC, DRC, Custom Layout, LVS, Cadence Virtuoso, Analog Layout Design
Skills:
Vdc, custom analog layout design, EDA Tools, Antenna, ADC, Circuit Design, RV high voltage flows, noise fixes, LDO, layout validation, Charge pump, density, DRCs, scripting skills, Vlsi Design, Virtuoso XL
