Greetings From LanceSoft
Location: Penang
Onsite Setup
Role: Senior Engineer
Key Responsibilities include
- Synthesis, LEC, Low power checks, Memory BIST insertion, Constraints validation.
- Collaborate with RTL designers, physical design, and DFT teams to ensure early detection and resolution of issues related to synthesis, constraints, and timing.
- Communicate effectively with all stakeholders across the organization
- Running RTL Lint, CLP, BIST, DFT insertion etc.
- Perform full-chip, Subsystem and block-level STA.
- TCL script development in addition to running/analyzing/debugging designs.
- Hands on with DC/Genus/Fusion Compiler, PrimeTime/Tempus, Formality/Conformal
- Mentor and train team members on early-stage implementation flows, tools, and best practices.
- Experience with either RTL development or Physical Design is also a plus.
Required Qualifications
- Bachelor's or master's degree in engineering with 5+ Years of experience.
- Should have strong understanding Synthesis methodologies with leading industry standard tools.
- Experience with writing timing constraints for synthesis, STA & PD.
- Perform full-chip and block-level STA using PrimeTime or Tempus.
- Experience with scripting language such as Perl/ Python, TCL.
- Able to work independently with design, DFT and PD team for netlist delivery, timing constraints validation.
- Able to handle ECOs and Logic Equivalence checking(LEC).
Preferred Qualifications
- Familiarity with DFT.
- Familiarity with power estimation with vectors, and UPF (unified power format).
- Familiarity with additional EDA tools.
- Utilize prompt engineering to:
- Generate EDA scripts
- Interpret timing reports
- Assist in ECO generation
- Use AI-driven tools for report generation, analysis, and knowledge capture.
