Job Title: Staff / Senior Design Verification Engineer
Job Location: Penang
Job Responsibilities:
- According to the design requirements, architecture, and specifications, develop verification plans and schedules
- According to the verification plan and schedule, set up an IP or SoC verification environment, develop and debug verification cases, checker mechanisms, etc
- Analyze and locate the reasons for the test cases failure, assist designers in locating and solving problems
- Test cases regression, collect and analyze code and functional coverage, and achieve coverage convergence
- Verification quality activity inspection, ensure verification completeness, and output verification report
- Improve verification efficiency, such as developing verification components, automating verification scripts, and implementing efficient verification methods
Job Requirements:
- More than five years of verification work experience, with rich experience in IP or SoC verification, familiar with the verification process
- Proficient in Verilog, system Verilog, proficient in scripting languages such as Perl and Python is preferred
- Proficient in UVM verification methodology, be able to independently build and debug IP or SoC validation environments
- Strong initiative, sense of responsibility, serious and meticulous work, and good teamwork spirit Priority will be given to those who meet the following conditions:
- Controller or PHY (SerDes, PCIE, DDR, HBM, etc.) verification experience with
- High-speed interfaces is preferred for admission
- Experience in verifying CPUs such as ARM or RISCV is preferred for admission
- Experience in verifying on-board MCU or AI SoC is preferred for admission
- Experience in verifying efficiency improvement, priority admission
