Senior Design Verification Engineer

Position: Design Verification Engineer

Location: Penang

Requirements:

• Digital ASIC/SOC design verification. The candidate should have good understanding on ASIC/SOC design flow and should have:
• Strong coding with Verilog and SystemVerilog
• Good knowledge of design verification methodology UVM.
• Many experiences with sequence creation, functional cover groups and assertion coding.
• Strong C/C++ software development experiences
• Be familiar with scripting language, such as Perl, C shell, Makefile, Ruby.

Plus skills:

• Has one or more of the following experience/knowledge.
• Such as X86/ARM/8051 architecture, AMBA(AXI/AHB/APB) bus, USB(3.0/2.0/1.1;
• SSIC/HSIC/host/device/OTG) system, NAND Flash host controller/BCH/double-data-rate interface, Universal Flash Storage, PCI-E/PCI bus, low power design, clock generation and control, SD/eMMC host controller, SATA/SAS, Legacy IPs (SPI/SMBUS/ACPI/LPC/GPIO), General connectivity IPs (I2S/I2C/UART), Ethernet, JTAG, etc.
• Exhibit good verbal and written communication skills in English

Responsibility:

• Will apply current functional verification techniques to perform and improve pre-silicon verification quality and product Time to Market for ASIC/SOC design.
• Be able to work independently on various DV tasks and providing technical guidance to the DV team.
• Involve technically in the porting/creation of the DV environment for the new design, block and chip level test plan creation and implementation, coverage analysis, and regression cleanup.