Senior DFT Engineer

DFT architecture, coverage analysis, Memory-BIST, ATPG pattern generation, compression at core level, Scan Insertion, SSN architecture, clock architecture, timing simulations, no-timing simulations, occ

simulation and verification flow, DFT design and verification, silicon bringup, DFT technologies, fault modeling, ASIC DFT synthesis, IP integration, DFT specification definition, silicon debug activities

Logic Design, On-chip scan compression, Scan BIST, Fault Simulation, ATPG

bist , Perl, Debugging, Python, Tcl, Logic Design, Sta, RTL, Scan, make, tessent, on-chip scan compression, gate level simulation, Fault Models, automation methods, ATPG, pattern generation, VLSI simulation tools, Fault Simulation