SENIOR ENGINEER, DESIGN AUTOMATION METHODOLOGIES

Vc, Perl, Verilog, Python, System Verilog, Tcl, LINT, cdc, Vlsi, front-end design verification techniques, formal verification tools, LEC, spyglass, FV, Synthesis, RDC, Design Compilers, EDA Tools, ASIC Design

technical compliance , System integration, Solution Design, Quality, ETO engineering, Application Engineering, Risk assessment methodologies, Engineering standards, Cooling technologies

Verilog, Usb, Tcl, Arm, System Verilog, Ethernet, Perl, Spi, I2c, Python, Soc Architecture, LINT, ASIC design flow, Timing Analysis, peripheral IPs, Synthesis, Low-power design, Axi, power estimations, BUS Protocols, MBIST, Bus Matrix design, MIPS, AMBA, Rtl Design, timing constraint SDC, DFT concepts, RDC, Formal CDC

Bonding System, CYMCAP, HV cable design, Earth Continuity, Project management, Installation testing and maintenance, Co-Axial Cable, Short circuit calculations, Cable sizing and insulation specifications, Report Preparation, Technical problem-solving, Site surveys and assessments, Compliance with standards and regulations, Quality control checks, Cable Modelling Software, Health Safety compliance, Cable Bonding layout

static timing analysis, Digital Logic Design, Perl, Verilog, Python, Scripting, Tcl, Synthesis, cdc, memory subsystems, SOC design, Uvm, IP integration, systemverilog, Rtl Design, Axi, formal verification, EDA tool flows, LINT, Verification, Microarchitecture, bus architectures, automation of design flows