Senior IP / Subsystem Pre-silicon Validation Engineer

Location (on-site): Malaysia (Penang)

Click on the link to APPLY: https://lnkd.in/gg595AaK

Role Summary

We are looking for an experienced Senior Validation Engineer to lead the functional verification and validation of complex SoC/IP designs. The ideal candidate will be responsible for defining the verification strategy, developing comprehensive verification plans, driving UVM-based verification environments, and ensuring high-quality silicon through thorough functional validation.

Key Responsibilities

• Drive the overall functional verification strategy for IP and SoC projects from planning to sign-off.

• Develop comprehensive verification plans based on design specifications, architecture documents, and customer requirements.

• Define verification methodologies, coverage goals, and regression strategies to achieve verification closure.

• Design, develop, and maintain SystemVerilog/UVM verification environments, reusable verification components, and testbenches.

• Create directed and constrained-random test cases to validate functional correctness and corner-case scenarios.

• Review design specifications and provide feedback to improve design quality and testability.

• Work closely with RTL designers, architects, and firmware teams to understand design intent and resolve functional issues.

• Analyze simulation failures, debug complex functional problems, identify root causes, and drive issues to closure.

• Monitor and report verification progress, coverage metrics, bug status, and verification sign-off readiness.

• Drive code coverage, functional coverage, assertion coverage, and verification closure activities.

• Mentor junior validation engineers and promote verification best practices across the team.

• Contribute to the continuous improvement of verification methodologies, automation, and reusable verification IP.

Qualifications

• Bachelor's or Master's degree in Electrical/Electronic Engineering, Computer Engineering, or related field.

• At least 3-10 years of experience in ASIC/SoC functional verification.

• Strong understanding of SystemVerilog and UVM (Universal Verification Methodology).

• Proven experience in developing UVM testbenches, sequences, scoreboards, monitors, agents, and reusable verification components.

• Able to independently write verification plans and translate design specifications into executable test scenarios.

• Strong knowledge of constrained-random verification, functional coverage, assertions (SVA), and coverage-driven verification.

• Experience debugging RTL using industry-standard simulators such as Synopsys VCS, Cadence Xcelium, or Siemens Questa.

• Familiarity with common on-chip protocols such as AXI, AHB, APB, PCIe, UCIe, USB, Ethernet, or DDR is an advantage.

• Strong debugging, analytical, and problem-solving skills.

• Excellent communication skills and ability to lead technical discussions across cross-functional teams.

• Experience mentoring junior engineers is highly desirable.

• Experience with scripting languages such as Python, Perl, Shell, or Tcl is a plus.

Preferred Qualities

• Self-driven and capable of owning the verification effort for an IP or SoC subsystem.

• Strong leadership in driving verification direction rather than only executing assigned tasks.

• Able to identify verification gaps, propose improvements, and establish best practices.

• Passionate about quality, automation, and continuous process improvement.