Senior / Lead Physical Design Engineer (Backend Implementation)

️ HIRING: SENIOR / LEAD PHYSICAL DESIGN ENGINEER (NETLIST-TO-GDSII) ️

Are you a master of silicon physical implementation who can take a raw logical netlist and transform it into production-ready GDSII silicon We are seeking an elite Senior / Lead Physical Design Engineer to take structural and physical ownership of complex, high-performance digital ASIC designs!

This is a heavyweight backend implementation seat. We are explicitly searching for engineers who have commanded full chip-level flows on deep sub-micron nodes, resolving complex routing congestion, executing clock tree synthesis ($CTS$), and mastering physical verification signoff.

Role Overview:

• Position: Senior / Lead Physical Design Engineer (Backend Implementation)
• Experience Baseline: 7+ Years of dedicated, hands-on ASIC Physical Design experience
• Node Geometries: Exposure to advanced process technologies ($14nm / 7nm / 5nm$ or below)
• Primary EDA Arsenal: Cadence Innovus, Synopsys ICC2, PrimeTime, Calibre, Voltus/PTPX
• Location: Kuala Lumpur, Malaysia / Regional Semiconductor Hub

️ Your Core Backend Mission:

• Full Netlist-to-GDSII Execution: Own the complete end-to-end physical design flow, spanning Floorplanning, Power Grid Design ($IR-Drop$), Placement, Clock Tree Synthesis ($CTS$), and complex Routing.
• Top-Level Integration & Signoff: Drive Top-level physical design construction, managing chip-level multi-mode multi-corner layouts and Top STA path closures.
• Rigorous Physical Verification: Execute exhaustive signoff gate-checks using Calibre for Design Rule Checks (DRC), Layout Versus Schematic (LVS), and Antenna rules.
• Power Dynamics & Extractions: Run static and dynamic power integrity reviews (Voltus / PTPX) alongside precise parasitic extractions (StarRC / QRC).
• Low-Power Frameworks: Integrate complex low-power design configurations using Unified Power Format (UPF) architectures across multiple switchable voltage islands.
• Cross-Functional Handoffs: Collaborate closely with frontend RTL, timing signoff, and DFT infrastructure engineering tracks to guide post-layout timing loops and ECO (Engineering Change Order) implementation.

How to Apply:

Ready to pave the physical future of next-generation silicon If you possess the 7+ years of Netlist-to-GDSII flow ownership and advanced node exposure required, please send your technical resume directly to:

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