SENIOR / LEAD STA & TIMING SIGNOFF ENGINEER

HIRING: SENIOR / LEAD STA & TIMING SIGNOFF ENGINEER

Are you the ultimate gatekeeper of silicon timing closure Do you know exactly how to squeeze out setup and hold violations on advanced process nodes ($7nm / 5nm$ and below) We are looking for a heavyweight Senior / Lead Static Timing Analysis (STA) Engineer to take complete ownership of our full-chip timing signoff pipeline!

This is a dedicated, highly specialized signoff seat. We aren't looking for pure RTL writers or layout generalists—we need a PrimeTime master who can look at complex multi-mode multi-corner ($MMMC$) environments, dissect tangled $SDC$ constraints, and confidently drive the chip to a flawless tape-out.

Role Overview:

• Position: Senior / Lead STA & Timing Signoff Engineer
• Experience Baseline: 5+ Years of dedicated, hands-on STA track record
• Core Weapon of Choice: Synopsys PrimeTime (or equivalent elite STA toolsets)
• Node Complexity: Exposure to advanced sub-micron process geometries ($7nm / 5nm / 3nm$)
• Location: Kuala Lumpur, Malaysia / Regional Tech Hub

️ Your Core Silicon Mission:

• Full-Chip Signoff Ownership: Drive timing convergence from block-level modules all the way to complex, top-level full-chip signoff.
• Constraint Hegemony ($SDC$): Author, debug, and systematically validate complex $SDC$ constraints, ensuring clean clock definitions, false paths, and multicycle path declarations.
• Advanced Node Optimization: Independently diagnose and resolve complex timing violations (Setup, Hold, Recovery, Removal, and Crosstalk/Noise) while accounting for variations on advanced sub-7nm process nodes.
• Cross-Functional Bridge: Serve as the central debugging hub—working hand-in-hand with Front-End RTL, Physical Design (P&R), and DFT engineering groups to resolve structural blocks.
• ECO & Synthesis Flow Design: Lead timing correlation and timing-driven ECO (Engineering Change Order) generation loops to implement fixes without breaking structural layouts.
• Scripting & Automation: Maintain, optimize, and build out automated script structures (Tcl/Perl/Python) to accelerate the team's internal STA workflows.

How to Apply:

Ready to sign off on next-generation silicon If you possess the 5+ years of full-chip PrimeTime timing closure experience required, please send your technical CV directly to:

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