Senior Physical Design Engineer
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Job Description – Physical Design Engineer
ACL Digital is hiring experienced Physical Design Engineers for our growing VLSI team.
Position
Physical Design Engineer
Experience: 6+ Years
Job Locations
Job Responsibilities
Required Skills
Qualification
Notice Period: Immediate to 30 days preferred
Interested candidates can share their updated resume to: [[Confidential Information]]
#Hiring #PhysicalDesign #ASIC #VLSI #Semiconductor #ICC2 #Innovus #STA #ACLdigital
Job ID: 148676027
Skills:
routing, Sta, CTS, ECO execution, Pv, floorplanning, Dfm, constraints synthesis, Dft, Si, Timing Closure, block-level PnR, Netlist to GDS flow
Skills:
Scripting, Perl, Tcl, Calibre, Innovus, Assura, Cv, ICC2, Cadence, EDA Tools, Verification Tools
Skills:
redhawk , Tcl, Perl, Python, SDC, Foundry PDKs, Implementation tool suite, EDA Tools, Power gating, Cadence, primetime, Tempus, Synopsys ICC2, CPF, Timing Analysis, TSMC, Physical Design, Synopsys, UPF, Cadence Innovus, Sta, Multi-voltage domains, Voltus, Signoff tools, Samsung, Low-power design techniques
Skills:
redhawk , Routing, Perl, Python, Tcl, SDC constraints, Design Compiler, CTS, primetime, Fusion Compiler, RTL-to-GDS implementation, Voltus, ECO implementation, Full Chip Physical Design, Synthesis, MCMM timing closure, Physical Design methodologies, EM IR analysis, Synopsys ICC2
Skills:
Tcl, Routing, Perl, Netlist2GDSII Implementation, Power Integrity Analysis, primetime, Floor Planning, Physical Verification, Cadence Tools, Calibre, CTS, Innovus, Sta, ICC2, Physical Design Methodologies, Tk, Placement, PT-PX, sub-micron technology
