Senior Physical Design Engineer
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Experience - 7+years
Location - Hyderabad, Bangalore, Pune and Kochi
Notice Period - Immediate to 60 Days
JD Physical Design -
• In-depth knowledge and hands-on experience on Netlist2GDSII Implementation i.e. Floor planning, Placement, CTS, Routing, STA, Power Integrity Analysis, Physical Verification.
• Should have experience on Physical Design Methodologies and sub-micron technology of 28nm and lower technology nodes.
• Should have experience on programming in Tcl/Tk/Perl.
• Must have hands-on experience on Synopsys/Cadence tools. (Innovus, ICC2, Primetime, PT-PX, Calibre).
• Well versed with timing constraints, STA and timing closure.
• Inspirational leadership style, good communication skills, and ability to work in a global environmentIn-depth knowledge and hands-on experience on Netlist2GDSII Implementation i.e. Floor planning, Placement, CTS, Routing, STA, Power Integrity Analysis, Physical Verification
• Should have experience on Physical Design Methodologies and sub-micron technology of 28nm and lower technology nodes.
• Should have experience on programming in Tcl/Tk/Perl · Well versed with timing constraints, STA and timing closure.
• Inspirational leadership style, good communication skills, and ability to work in a global environment.
Job ID: 145164359
Skills:
routing, Sta, CTS, ECO execution, Pv, floorplanning, Dfm, constraints synthesis, Dft, Si, Timing Closure, block-level PnR, Netlist to GDS flow
Skills:
Scripting, Perl, Tcl, Calibre, Innovus, Assura, Cv, ICC2, Cadence, EDA Tools, Verification Tools
Skills:
redhawk , Tcl, Perl, Python, SDC, Foundry PDKs, Implementation tool suite, EDA Tools, Power gating, Cadence, primetime, Tempus, Synopsys ICC2, CPF, Timing Analysis, TSMC, Physical Design, Synopsys, UPF, Cadence Innovus, Sta, Multi-voltage domains, Voltus, Signoff tools, Samsung, Low-power design techniques
Skills:
redhawk , Routing, Perl, Python, Tcl, SDC constraints, Design Compiler, CTS, primetime, Fusion Compiler, RTL-to-GDS implementation, Voltus, ECO implementation, Full Chip Physical Design, Synthesis, MCMM timing closure, Physical Design methodologies, EM IR analysis, Synopsys ICC2
Skills:
Tcl, Routing, Perl, Netlist2GDSII Implementation, Power Integrity Analysis, primetime, Floor Planning, Physical Verification, Cadence Tools, Calibre, CTS, Innovus, Sta, ICC2, Physical Design Methodologies, Tk, Placement, PT-PX, sub-micron technology
