KEY RESPONSIBILITIES:
Silicon Characterization & Debug:
- Lead the development and execution of comprehensive characterization plans across PVT corners.
- Analyze complex electrical behaviors, parametric shifts, system sensitivities, and failure signatures.
- Drive root-cause investigations and collaborate with design, test, and diagnostics teams to close issues.
Yield Engineering:
- Own yield learning for early silicon; identify systemic issues, propose fixes, and validate improvements.
- Track and interpret yield trends across defectivity, structural, and parametric components.
- Guide test content owners on pattern health, coverage gaps, and debug prioritization.
Product Definition:
- Define or refine OPNs, fuse maps, binning schemes, performance/power guard-bands, and speed-bin rules.
- Align product definition with business goals, technical feasibility, and manufacturing capability.
- Partner with cross-functional teams to ensure final definitions translate to robust distribution and yield targets.
Technical Leadership & Collaboration:
- Mentor PDE1/PDE2 engineers in debug, data analysis, and test methodologies.
- Provide technical guidance across multiple feature domains or product lines.
- Drive clear communication in line with product milestone reviews.
PREFERRED EXPERIENCE:
- Extensive silicon bring-up experience, including leading debug for complex electrical issues and multi-domain interactions.
- Proven yield analysis expertise, with ability to identify patterns, systematics, and root causes in early ramp phases. Experience owning or contributing to product binning, OPN strategy, guard-band tuning, or power/performance correlation.
- Strong background in data automation, statistical modeling, or production analytics pipelines.
- Experience optimizing or architecting test flows, debug infrastructure, or test content strategies.
- Cross-functional leadership experience in working with design, test development, diagnostics, foundry, reliability, or device analysis teams.
- Track record of driving improvements in test time, yield, coverage, or debug efficiency through innovation or process enhancements.
- Ability to act as a technical mentor, guiding junior engineers in analysis, methodology, and best practices.
