We're expanding our SoC DFX team and hiring across three specializations: Scan/ATPG, Memory BIST (SMS), and Timing Signoff. This role sits within the SoC design and DV flow, working on both pre-silicon design/verification and post-silicon ATE debug and bring-up. Depending on your background, you'll be aligned to one of the following tracks:
- Scan/ATPG: tile and chip-level scan insertion, ATPG, and scan pattern simulation, plus post-silicon Scan ATE testing and silicon debug
- SMS (Memory BIST): MBIST design and verification for SRAM, ROM, and latch arrays, memory repair test development, and production test optimization
- Timing Signoff: full-chip test mode timing signoff, SDC quality checks, and cross-die STA activities
Responsibilities
- Study and implement cutting-edge test strategies within your specialization
- Scan track: own tile-level scan insertion, ATPG, and quality checks; perform scan DRC and non-scan analysis; generate and verify chip-level scan patterns; support Scan ATE bring-up and debug
- SMS track: implement DFX SMS design on SRAM/ROM/latch arrays; develop and verify tile- and chip-level BIST and memory repair test cases; develop high-coverage, cost-effective production test patterns
- Timing track: develop and maintain DFT SDC; support special and multi-voltage timing checks; enhance timing signoff automation; work with Front-End and Physical Design teams on synthesis optimization and full-chip timing closure
- Collaborate across Front-End Design, Physical Design, DV, and DFT teams to support product delivery milestones
- Support DFX quality checks, documentation, and silicon bring-up activities
Requirements
- Bachelor's degree with 3 years, or Master's degree with 1 year, of relevant experience, minimum
- Minimum 5 years of experience in one or more of: MBIST, DFT/DFX, scan insertion, ATPG, STA/timing signoff, synthesis, SoC verification, or related semiconductor design activities
- Solid background in process, device, or ASIC design
- Proven knowledge in two or more of: SCAN, MBIST, RTL design, STA, Verification, or DV
- Strong programming/scripting skills in Perl, Tcl, or Python is a strong plus
- Familiarity with JTAG, Boundary Scan, Design Compiler/Fusion Compiler/Primetime, or CTS/ICC physical design flow is a plus, depending on track
- Good communication skills in English (Mandarin a plus); self-driven, collaborative, and willing to learn/share
