We are hiring Senior Staff / Staff / Senior / Junior SoC RTL Design Engineer
(Multiple positions available)
Job Highlights
- Exciting future with breakthrough technologies
- Great career growth opportunity in a leading RISC-V technology
- Attractive compensation & benefits package with stocks
Job Description:
- Responsible for RISC-V based SoC RTL design integration.
- Perform SoC and IP subsystem RTL design integration which includes integration of key SoC IP subsystems & peripherals block .
- Develop SoC integration and technical reference manual documentation.
- Perform IP logic design on SoC required adaptation logic blocks.
- Collaborate with Verification & FPGA engineers on functional/performance/integration simulation validation, FPGA prototyping and debug.
- Perform front end quality checks ranging from RTL static & synthesizability checks, timing convergence, netlist quality checks and etc.
- Optimize & maintain SoC RTL integration flow & scripts.
- Work with Software Development Team on firmware driver and software requirements.
Requirements:
- Bachelor / Master degree in Electrical & Electronic Engineering, Computer Engineering or equivalent.
- Experience in SoC and/or IP logic design implementation and/or verification .
- Experience with Verilog and System Verilog RTL.
- Familiar with EDA tools such as Xcelium/Modelsim/VCS, Spyglass, industry leading logic synthesis and logic equivalency checks tools.
- Knowledge in RISC-V / ARM architecture, AMBA/AXI protocol, interconnects and various IP Protocol.
- FPGA prototyping and scripting skills in Perl, tcl, Python & shell is an added advantage.
- Strong problem solver, good communication skills and team player.
- 12 years of relevant experience on SoC RTL integration or IP logic design for Senior Staff position, 8 years for Staff position, 5 years of relevant experience for Senior position.
